Processors are utilized in various applications. A standard configuration is to couple a processor with a storage unit, such as a cache, a system memory, or the like. Processors may execute a fetch operation to fetch instructions from the storage unit as needed. A processor pipeline includes several stages for processing instructions. In one implementation, a four stage pipeline may be used, and includes a fetch stage, a decode stage, an execution stage, and a write-back stage. Instructions progress through the pipeline stages in order.
To speed up the operation of the processor, it is desirable to have a full pipeline. One way of filling the pipeline is to fetch subsequent instructions while previous instructions are being processed; this is known as “pre-fetching” an instruction. “Speculatively executing” an instruction means that a subsequent instruction in the pipeline to be executed may be the wrong instruction (based on a branch misprediction, for example) or may not be ready for execution because the instruction is dependent on the result of a prior instruction. Although pre-fetching and speculatively executing the instructions may result in speeding up the instruction processing, it may have the opposite effect and may result in stalling the pipeline if the branch direction is mispredicted or the dependent instructions are not ready for execution. If a branch misprediction occurs or an instruction is not ready for execution, the pipeline needs to be flushed and the instructions will need to be re-executed (i.e., replayed). This may negatively impact the performance of the system.
A replay scheduler may speculatively execute an instruction based on an assumption that data is located in a cache. Existing schedulers which support replays based on data cache speculation have limited visibility into the confidence of the data speculation. If the data is not in the cache (i.e., the data cache speculation fails), the scheduler may unnecessarily wakeup several dependent operations, wasting power and issue bandwidth.